Typically, a CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, a photoconductor, or a photodiode. A readout circuit connected to each pixel cell typically includes at least an output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region, connected to the gate of a source follower output transistor. A charge transfer device can be included as well and may be a transistor for transferring charge from the photoconversion device to the floating diffusion region. Imager cells also typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
FIG. 1 illustrates a block diagram of a CMOS imager device 308 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row selected line, and the pixels of each column are selectively output by respective column select lines. A plurality of rows and column lines are provided for the entire array 200. The row lines are selectively activated by the row driver 210 in response to row address decoder 220 and the column select lines are selectively activated by the column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the control circuit 250 which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout, and row and column driver circuitry 210, 260 which apply driving voltage to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal, Vrst and a pixel image signal, Vsig, are read by a sample and hold circuit, 261, 262 associated with the column device 260 and a differential signal Vrst—Vsig is produced for each pixel which is amplified and digitized by analog to digital converter 275. The analog to digital converter 275 converts the analog pixel signals received from the column driver 260 and its associated sample/hold circuits 261,262 to digital signals which are fed to an image processor 280 to form a digital image.
A conventional CMOS image sensor pixel array usually follows a typical Bayer pattern as shown in FIG. 2 with one pixel for each of the colors red 82, green 87, and blue 83, respectively and arranged in a mosaic pattern as shown. Since there is only one pixel per color, the array requires a larger surface area. Another type of pixel, shown in FIG. 3, is a pixel which attempts to minimize array area by detecting all three colors at differing depths in a silicon substrate. See U.S. Patent Publication No. 2002/0058353. One detriment of placing photoconversion regions for all three colors in one pixel is that the colors cannot, in practice, be completely separated and discerned by the stacked photoconversion regions, even when they are placed at optimal depths based on light wavelength. This incomplete color separation results in cross talk between adjacent color detection regions and poor quantum efficiency.